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Altera_Forum's avatar
Altera_Forum
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12 years ago

ALTPLL output directly to FPGA's pin

Hi,

I know this question has been asked in different forms many times now but I don't get what happens in my case since I seem to do everything right. I'm using the DE0 Development and Education Board equipped with a Cyclone III EP3C16. I have the 50 MHz clock input on G21 (optional function CLK4). I configured a PLL to output a 1 MHz clock on c0 output and connected c0 directly to pin AA3 (dedicated pin PLL1_CLKOUTp).

When I compile I get the well-known warning from the fitter:warning (15064): pll "clock_ccd:clock_ccd_inst|altpll:altpll_component|clock_ccd_altpll:auto_generated|pll1" output port clk[0] feeds output pin "gpio0_clkout[0]~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. use pll dedicated clock outputs to ensure jitter performance

Can someone explain why? I seem to use the dedicated outputin pin for PLL, I use c0 so what is wrong?

Thank you,

Sebastian

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    CLK4 can't feed PLL1 directly. Do you really worry about some picoseconds extra jitter of a 1 MHz clock?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Yes CLK4 can't feed the PLL1 directly but that shouldn't affect the output of the PLL, should it? But because I saw this I used another megafunction for another clock (this should use PLL2 now that PLL1 is used) and I got the same warning.

    I understand this is a small jitter compared to the clock's frequency but still, I want to understand how it works.

    Thanks,

    Sebastian