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Altera_Forum's avatar
Altera_Forum
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12 years ago

ALTPLL output directly to FPGA's pin

Hi, I know this question has been asked in different forms many times now but I don't get what happens in my case since I seem to do everything right. I'm using the DE0 Development and Educatio...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

CLK4 can't feed PLL1 directly. Do you really worry about some picoseconds extra jitter of a 1 MHz clock?