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Altera_Forum's avatar
Altera_Forum
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12 years ago

ALTPLL output directly to FPGA's pin

Hi, I know this question has been asked in different forms many times now but I don't get what happens in my case since I seem to do everything right. I'm using the DE0 Development and Educatio...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Yes CLK4 can't feed the PLL1 directly but that shouldn't affect the output of the PLL, should it? But because I saw this I used another megafunction for another clock (this should use PLL2 now that PLL1 is used) and I got the same warning.

I understand this is a small jitter compared to the clock's frequency but still, I want to understand how it works.

Thanks,

Sebastian