Honored Contributor
Honored ContributorPin AE31 also isn't a dedicated PLL clock input. The Stratix III pinout files and DE340 user manuals clearly tells, which pins can be used as clock input. C26 in contrast is a LVDS receiver pin according to the pin-out file, so the reported error message isn't understandable to me unlesse you selected a different part than EP3SL340H1152. Or the pin-out file would be wrong.
Another point is selection of PLLs by Quartus. Normally they are selected based on the pin assignments. In some cases, e. g. when chaining PLLs, this automatic selection fails, then you have to select the correct PLL manually by assigning a location to the instance in assignment editor. Serialisation/Deserialization in LEs is always an option for lower bitrates. However the DE340 HSTC connector pin mapping is intended to use dedicated LVDS hardware. As far as I saw, it is basically correct.
