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Altera_Forum's avatar
Altera_Forum
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17 years ago

altpll function

I am using Terasic DE3 340 board which supports LVDS input and output. When I assigned the location for altpll input as a specific pin in Assignment Editor, it gave the following error on compilin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Which datasheet are you looking at? I'm guessing it's the Terasic datasheet? That probably doesn't have all the ports available on the FPGA, just the pins brought out on their board. But when you have a floating port(no location assignment), Quartus has no idea what your board is, and may use a port that isn't connected on the board.

How are you actually bringing the clock in? Is it something you're hooking up to a general I/O, or is it an existing clock on the board coming in(in which case you have no flexibility). Are you sure the board was designed for this interface?