altpll function

Don't lock it down and see where it puts it.

The LVDS blocks generally use a Fast PLL, which is a very low jitter, dedicated PLL to make your interface work. The timing is quite tight and needs a very strict relationship between clock and data(I say it's tight, but I actually don't know what speeds you're running at.) The Fast PLL has dedicated clock pins that drive it. If you bring the clock in on other pins, then they delay from that pin to the PLL will use local, non-compensated routing, rather than the path specifically laid out for this type of interface.