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sounds like you havent added the source file for the alt mult add to your project. WHat you show is just the component declaration.
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i have 2 files for the simulation:
1. test bench file, in which the component altmult_add is declared as:
component fakir_1_altmult_add_coef
PORT
(
aclr0 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
coefsel0 : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
dataa_0 : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;
and instanciated as:
fakir_1_altmult_add_coef_1: fakir_1_altmult_add_coef
port map (
aclr0 => reset_calc_signal,
clock0 => clk_signal,
coefsel0 => "000",
dataa_0 => dataa_0_signal,
datab_0 => dataa_1_signal,
ena0 => ena0_signal,
result => result_signal);
2. the megawizard generated .vhd file of this component.
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