Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHi std_logic_vector, thank you for your reply.
I am building for the Cyclone III and was not aware that it had that circuitry and so that is probably it, since imnmy simulation it was working even though I could not determine why. Unfortunately the FPD-Link specification requires 3 channels with a deserialization factor of 7 and so it must be odd, but it is simulating correctly as far as I can tell and so I am glad I now know why. (If I do run into any more problems are are also FPD-Link IP Cores so I may try one of those) Thanks for the tip about the RAM buffer, I'll see if I cant figure out how to disable its use. (This is the first time ive used ALTLVDS so Im just learning my way around it)