ALTLVDS CoreClk with Odd Deserialization Factors

Hi Sebastion,

Which FPGA do you use? Some families (like Cyclone III) have dual datarate input circuits, so that could be the reason for the frequency you mention. But that doesn't explain the odd/even difference.

In general, if you can avoid an odd serialization factor, do so. I've had a lot of trouble with it. See some recent theads at this forum. If you are sticked to an odd (de)serialization, at least do not use RAM as a buffer (tab 2 or 3 of the MegaWizard).

Succes, Ton