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Altera_Forum
Honored Contributor
11 years agoThanks for your answer, Tricky!
Thank you, Galfonz! I know about Vivado IP Integrator, but it is a high-level schematic, like QSYS schematic. Xilinx removed schematic from it's software, you can only observe RTL from HDL code and can't instantiate, for example, PLL at the top level as a schematic.