altera_sc_fifo problem - invalid first transfer

Actually - looking at your (small) picture and testbench code - I bet it's a delta race problem. Initial block uses# time intervals and is not synchronous to the clock - so the out_ready signal is actually 1 when the clock changes and hence you lose the first word. Change the control initial to use clocks instead of# timing statements:

task wait_for_clk(int n = 1);
	for(int i = 0; i < n ; i++) @(posedge clk);
endtask
	
initial 
begin
	clk = 1;
	resetn = 1;
	fifo_data = 64'haaaaaaaaaaaaaaaa;
	fifo_empty = 0;
	fifo_startofpacket = 0;
	fifo_endofpacket = 0;
	out_ready = 0;
	fifo_valid = 0;
	
# 30
		resetn = 0;
# 50
		resetn = 1;
		
	//resyncrhonise to the clock
	wait_for_clk(4);
		fifo_valid = 1;
		fifo_startofpacket = 1;
	wait_for_clk;
		fifo_data = 64'hbbbbbbbbbbbbbbbb;
		fifo_startofpacket = 0;
	wait_for_clk;
		fifo_data = 64'hcccccccccccccccc;
	wait_for_clk;
		fifo_data = 64'hbbbbbbbbbbbbbbbb;
	wait_for_clk;
		fifo_data = 64'hdddddddddddddddd;
		fifo_endofpacket = 1;
	wait_for_clk;
		fifo_endofpacket = 0;
		fifo_valid = 0;
	wait_for_clk(5);
		out_ready = 1;
	
end