Altera PLL and SDC timing constraints for Timequest

hi all,

I have to connect an asychronous SRAM, the Address to Data valid (read cycle) is 12ns.

I want to check the path delay: address_register -> SRAM_ADDRESS pins -> device 12ns tpd -> SRAM_DATA pins -> data_register

will be lower than 20ns (2 cycles of my sys_clk).

1. how I define the output address pind to input data pins delay (12ns of the sram)?

2. how I ask the SDC to check the delay of the path I described?

thanks alot,

Eli