Altera PLL and SDC timing constraints for Timequest

Maybe this reply is too late for bcao, just for anyone else seeing this thread...

the creat_generated_clock in the 3rd line is redundant, 'cause derive_pll_clocks already creates all the generated clocks at the PLL outputs for you.

With the creat_generated_clock in the 3rd line, TimeQuest thinks you have another clock called "sram_clk_pin", which is generated from the output clk[2] of PLL, although you specify the source and target as the same. Therefore, you need an additional set_clock_groups to separate it from clk[0].