Altera PLL and SDC timing constraints for Timequest

Hi

In a simple project,

derive_pll_clocks

set sram_clk inst|the_pll|the_pll|altpll_component|pll|clk[2]

create_generated_clock -name {sram_clk_pin} -source inst|the_pll|the_pll|altpll_component|pll|clk[2] -offset 0.500 [get_ports {sram_clk}]

set_clock_groups -exclusive -group [get_clocks {inst|the_pll|the_pll|altpll_component|pll|clk[0]}] -group [get_clocks {inst|the_pll|the_pll|altpll_component|pll|clk[2]}]

I got some warning message about unconstrained path. So I have to add the following line to get rid of the warning message.

set_clock_groups -exclusive -group [get_clocks {sram_clk_pin}] -group [get_clocks {inst|the_pll|the_pll|altpll_component|pll|clk[0]}]

The confusing thing is that the TimeQuest should be able to know that any paths related to inst|the_pll|the_pll|altpll_component|pll|clk[2] are independent of inst|the_pll|the_pll|altpll_component|pll|clk[0]}] by setting clock groups the first time. Why should I set clock groups twice?

Many thanks.