Altera PLL and SDC timing constraints for Timequest

Probably too late for Cyclone to care, but in case anyone else sees this thread...

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e.g. set_false_path -from [get_clocks {can_pll|altpll_component|pll|clk[0]}] -to [get_clocks {can_pll|altpll_component|pll|clk[2]}]

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This set_false_path exception is OK if the design does not require these cross-domain paths to be synchronous, but typically for cross-domain paths the set_clock_groups command is used instead. set_clock_groups cuts all paths in both directions between the clock domains.

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Further more I defined such timings

# **************************************************************

# Set Maximum Delay

# **************************************************************

# Tco

set_max_delay -from [get_registers *] -to [get_pins *] 10

# Tsu

set_max_delay -from [get_pins *] -to [get_registers *] 10

# Tpd

set_max_delay -from [get_pins *] -to [get_pins *] 10

# **************************************************************

# Set Minimum Delay

# **************************************************************

# Th

set_min_delay -from [get_pins *] -to [get_registers *] 10

The problem is that I still got hold time errors. And I´m not sure why!? Compiling with physical synthesis does not improve the behaviour.

2.) I still have a lot of unconstrained pathes. How can I get all pathes constrained without typing hundred lines like that:

set_min_delay -from [get_clocks *] -to [get_pins *] 10

set_min_delay -from [get_pins *] -to [get_ports *] 10

set_min_delay -from [get_ports *] -to [get_ports *] 10

set_min_delay -from [get_ports *] -to [get_pins *] 10

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You have a mix of get_pins and get_ports. I wonder if you intended all these constraints to be for device pins. For those, you use only get_ports. The get_pins collection is internal points in the design (like a LUT input or a register output), not device pins.

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The problem is that I still got hold time errors. And I´m not sure why!? Compiling with physical synthesis does not improve the behaviour.

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I doubt that physical synthesis does anything for hold timing. Make sure you have "Optimize hold timing" enabled in the Fitter Settings. If you have violations on internal paths and if those violations are not from a design problem like an avoidable gated clock, then set "Optimize hold timing" to "All Paths".