Altera PLL and SDC timing constraints for Timequest

OK I think that is clear to me :D Thanks so far!

I have 2 further questions:

1.) After defining all PLL clock input/outputs I got timing errors after synthesis (setup and hold time violations). Most violations was solved after defining the PLL outputs independend from each other:

e.g. set_false_path -from [get_clocks {can_pll|altpll_component|pll|clk[0]}] -to [get_clocks {can_pll|altpll_component|pll|clk[2]}]

Further more I defined such timings

# **************************************************************

# Set Maximum Delay

# **************************************************************

# Tco

set_max_delay -from [get_registers *] -to [get_pins *] 10

# Tsu

set_max_delay -from [get_pins *] -to [get_registers *] 10

# Tpd

set_max_delay -from [get_pins *] -to [get_pins *] 10

# **************************************************************

# Set Minimum Delay

# **************************************************************

# Th

set_min_delay -from [get_pins *] -to [get_registers *] 10

The problem is that I still got hold time errors. And I´m not sure why!? Compiling with physical synthesis does not improve the behaviour.

2.) I still have a lot of unconstrained pathes. How can I get all pathes constrained without typing hundred lines like that:

set_min_delay -from [get_clocks *] -to [get_pins *] 10

set_min_delay -from [get_pins *] -to [get_ports *] 10

set_min_delay -from [get_ports *] -to [get_ports *] 10

set_min_delay -from [get_ports *] -to [get_pins *] 10

I atteached my SDC

Thanks :confused: :( :p

CYCLONE