Forum Discussion
Altera_Forum
Honored Contributor
10 years agoIn the end I moved to Q15.0, and then regenerated the Qsys system for my design. When I recompiled it nocked 30MHz of the Fmax of several clock domains in the design. After two weeks optimising the code and having to enable all of the optimisation options (retiming, logic duplication, optimise for speed, etc.) I finally managed to get the design to meet timing in Q15. At least I can simulate the new FIR filter part of the design now.
Just to be really irritating, on the day I finally got the code to meet timing on Q15 and ensure that all my optimisations still function correctly... Q15.1 was released! Somehow I doubt I'll be upgrading if it's going to cost another 30MHz.