Altera FPGA ring oscillator low level implementation

One thing I like as an alternative to the LCELL is using a keep attribute. Open the VHDL/Verilog in Quartus and go to Edit -> Insert Template -> VHDL/Verilog -> Synthesis Attributes to find examples. You basically just create signals/wires in a chain and apply the keep, which forces each one to be the ouptut of an LCELL.

As for the question, I don't think it's in a datasheet. It's probably not a fixed number to begin with(i.e. it might vary within a device), but different devices, different speed grades could also cause differences. On top of that, each input through the LCELL has a different delay, which makes sense. Because of all this, it is not a fixed delay. (Note that you can lock down the placement and routing of a section in the design, and with everything physically locked, the timing can change by a few ps depending on what is placed and routed around it. This is accurate timing, but just another indicator of why timing is so hard to lock down to simple numbers...)