Altera FPGA ring oscillator low level implementation

I used LCELLs as inverter-buffers to create an RO. To analyze the delays I have left the chain open, and I am just studying the propagation delay of the chain. I plan to sample at 100MHz, so I want my osc to run at 10MHz. For this I need to calculate the number of invs I would need.

Here's the VHDL. Hacked Rysc's code from earlier in this thread.

***

USE IEEE.STD_LOGIC_1164.ALL;

LIBRARY IEEE;

ENTITY osc IS

PORT

(

din: IN STD_LOGIC;

dout, pin0, pin1, pin2 : OUT STD_LOGIC

);

END osc;

ARCHITECTURE arch OF osc IS

SIGNAL in0, in1, in2 : STD_LOGIC;

SIGNAL out0, out1, out2 : STD_LOGIC;

COMPONENT LCELL

PORT (

a_in : IN STD_LOGIC;

a_out : OUT STD_LOGIC);

END COMPONENT;

BEGIN

in0<= NOT din;

LC_0 : LCELL

PORT MAP (

a_in => in0,

a_out => out0);

pin0<=out0;

in1<=NOT out0;

LC_1 : LCELL

PORT MAP (

a_in => in1,

a_out => out1);

pin1<=out1;

in2<= NOT out1;

LC_2 : LCELL

PORT MAP (

a_in => in2,

a_out => out2);

dout <= out2;

END arch;

***

3 inverter-buffer LCELLs. Compiles well. Ignore LCELL buffers is off.

Here's the RTL view. Looks like I wanted it to be ~ link (http://img132.imageshack.us/img132/8985/delaychainzd1.gif)

[One odd thing is that the net name and the buffer names are the same? LC_0 appears in nets and buffers both]

Here's the waveform vector file ~ link (http://img403.imageshack.us/img403/2221/vvfiw6.gifhttp://img403.imageshack.us/img403/2221/vvfiw6.gif)

I run the simulation - this is what I see ~ link (http://img169.imageshack.us/img169/93/simulationtu2.gif)

Notice how changes on pin0 occur after nearly 10ns. But pin1 and pin2 change so very fast.

In an earlier code, dout transitioned even before pin0 and pin1 would. I am zapped. Am I doing something dreadfully wrong? How can I calculate the propagation delay :S ?