Altera FPGA ring oscillator low level implementation

It's not the cleanest code(a for-generate might work better), but it does do what you want. The instance names should be assignable too. Open the Assignment Editor, type LC_a in the To column, type Location in the Assignment Column, and then X5_Y5 in the Value(or whatever lab location you want), and you can assign to an individual node if you want.

You should also be able to put them all into a LogicLock region, so the fitter chooses their final placement within a lab and where the lab goes, but will keep them all in the same lab.

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY delay IS

PORT (

din : IN STD_LOGIC;

dout : OUT STD_LOGIC);

END delay;

ARCHITECTURE arch OF delay IS

SIGNAL a, b, c, d, e, f : STD_LOGIC;

COMPONENT LCELL

PORT (

a_in : IN STD_LOGIC;

a_out : OUT STD_LOGIC);

END COMPONENT;

BEGIN

LC_a : LCELL

PORT MAP (

a_in => din,

a_out => a);

LC_b : LCELL

PORT MAP (

a_in => a,

a_out => b);

LC_c : LCELL

PORT MAP (

a_in => b,

a_out => c);

LC_d : LCELL

PORT MAP (

a_in => c,

a_out => d);

LC_e : LCELL

PORT MAP (

a_in => d,

a_out => e);

LC_f : LCELL

PORT MAP (

a_in => e,

a_out => f);

dout <= f;

END arch;