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Each LAB has 32 LEs. LEs are either LUTs or Flip Flops.
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In Cyclone II, a LAB has 16 LEs. An LE is a LUT and register pair. The LUT and register can be used together or independently. Even if used separately, they are not counted separately for the LE quantity.
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High level idea of project:
Test for process variation of different chips.
...
Implementation:
... create multiple ring oscillators on the chip.
After the program runs various time delays will be obtained which can be used to draw conclusions regarding process variation of the chip.
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Your method should work well to compare delay of a ring at the same location on different devices for chip-to-chip process variation. If you are trying to measure process variation across the same device by comparing the ring delay in different locations, however, then you must avoid contributors to differences in the ring delay that will exceed the process difference.
Even if you have exactly identical placement of the LUTs with respect to each other in a given ring, you might not be able to have exactly the same routing resource usage in the connections. A small difference in routing resource usage could affect the ring delay by more than the process variation does.
Your rings could also have different delays because of different LUT inputs being used. The delay through the LUT depends on which input is used. When comparing more than one instance of a simple ring without other logic placed nearby, I would expect the same LUT position in the ring would use the same input for all ring instances. For example, buffer LUT# 1 might use input A for all rings, and the inverter LUT might use input C for all rings. However, you can't control that manually to guarantee it (unless you create a routing constraints file, which is probably more trouble than you would want). The Fitter will choose which LUT input is used during the routing stage.
Because you will have only 5 LUTs (4 buffers and an inverter) in each loop, you can keep each ring in a single LAB. I think keeping each ring within a single LAB will help make the routing the same if you can get the same exact relative placement within the LABs (the Assignment Editor has a "Comb. cell" location assignment type for Cyclone II). If the routing is the same from one ring to the next, then the same LUT input will be used for the same LUT position in the ring from one ring to the next. Look at the reported timing to see whether there are any ring-to-ring differences in the interconnect delay (to check for the same routing) or cell delay (to check for delay differences from which LUT input is used). You can also use the Chip Planner to view the routing that is used and the Resource Property Editor to see the exact LUT input that is used.
Be careful not to introduce measurement uncertainty by the method of measuring the delay through the ring. If, for example, you are going to use the ring signal to clock a counter, be careful that this additional logic does not cause the Fitter to make the ring instances different. I'd have the ring clock a single register in the same LAB and drive that register output to a counter that is far enough away it does not compete with the ring for routing resources. The less simple each instance is or the more nearby resources are used by other things, the more likely you'll run into differences in the specific LUT inputs and routing channels the Fitter chooses.
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