Altera_ForumHonored Contributor8 years agoaltera_attribute for regional_clock I am using a PLL and want to make sure (in VHDL) that the outputs of the PLL go to regional clock networks. Due to the PLL being an IP I can not add attributes to the rtl of the PLL. Thus I try to ad...Show More
Altera_ForumHonored Contributor8 years agoYes, manually edit your .qsf or use the Global Signal assignment in the Assignment Editor.
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