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Altera_Forum
Honored Contributor
Honored Contributoraltera_attribute for regional_clock
I am using a PLL and want to make sure (in VHDL) that the outputs of the PLL go to regional clock networks. Due to the PLL being an IP I can not add attributes to the rtl of the PLL. Thus I try to ad...
Altera_ForumHonored Contributor
Honored ContributorThe recognised way to do this is, as you've found, in the .qsf. Adding '|' symbols into your rtl files is going to cause issues.
See Altera's "how do i assign a clock in my design to use specific global, regional, dual-regional, or periphery clock networks? (https://www.altera.com/support/support-resources/knowledge-base/solutions/rd09282011_171.html)" support solution. Cheers, Alex
