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Honored Contributor
Honored ContributorAltclkctrl ip
Hi, I am using ALTCLKCTRL to mux two clock signals. One of the signal is a PLL output and the other one is an from the clock pin. I get an error from the fitter stating that it cannot place...
Altera_ForumHonored Contributor
Honored ContributorHi Rysc,
Sorry, I missed out on this thread as I was working on different things since quite some time. My apologies for the late response. I am using Cyclone-V, and as you suggested I looked at the device handbook. - https://www.altera.com/en_us/pdfs/literature/hb/cyclone-v/cyclone5_handbook.pdf In the clock control section, I see that inclk0, inclk1 can be driven by a dedicated clock pin, and inclk2,inclk3 can be driven by PLL outputs (depending on the counter# and placement coordinates of PLL). I fed the clock coming from a dedicated clock pin (to inclk0) and PLL output - counter4 (to inclk2) to the CLKCTRL block. I used chip planner to double check that the PLL is to the left side of cyclone V device. However, I still get the same placement error of the fitter not being able to place a global clock driver between the clock pin and the clkctrl block. Do you think I am doing anything wrong here? Your help is appreciated. Thanks, Vittal
