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Altera_Forum
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8 years ago

ALT_SLD_FAB Errors

Hello, I have been using FPGAs and CPLDs up to some extent in industrial applications. Just out of curiosity, I have been trying to implement a NIOS II system following the exact same steps in ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Thank you for the quick reply. In the design, SignalTap is turned off.

Just to see how it goes, I tried to generate a few different designs with Qsys. Other than NIOS II, I tried generating a Quad SPI controller, a Triple-Speed Ethernet, an SPI unit and an on-chip RAM block, just to see if Quartus will compile. Qsys successfully generated all the components and I added them to the top level .bdf file one at a time and run Analysis & Synthesis. Except for the SPI and RAM implementation, all the other attempts gave the same three error messages. SPI and RAM, on the other hand, were successfully synthesized. Apparently, it is not directly related to Qsys either.

I am using Quartus 15.0 Web Edition. Could this be a licencing issue?