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HongLiang's avatar
HongLiang
Icon for New Contributor rankNew Contributor
3 years ago

Aglix F-tile P&R error

we try to put an F-tile PHY into our design there are some error that occurs Error (22144): Cannot place the block dp_rx|rx_phy_top_inst|u_dp_gxb_rx|directphy_f_0|dphy_hip_inst|persystem[0].p...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

There are some rules to be followed for the F-tile. Please check following link: https://www.intel.com/content/www/us/en/docs/programmable/683872/22-3-4-2-0/f-tile-placement-rules.html


There are tools available for you to easily understand channel assignment as per your requirement. See following page: https://www.intel.com/content/www/us/en/docs/programmable/683872/22-3-4-2-0/supported-tools.html


Hope this helps. In case you still need help, please provide us with your design requirement along with the .ip file of the F-tile IP that you used.


Regards