aggregate not accepted

with the code you have:

(s2, s1) <= ('0', '0');

it has the choice of the following types:

std_logic_vector

unsigned

signed

string

bit_vector

+ some other type I cant think of.

To make this work, you need to tell the compiler what type you mean with a qualified expression:

(s2, s1) <= std_logic_vector'('0', '0');

Yesterday I tried something similar :

(s2, s1) <= (std_logic'('0'), std_logic'('0'));

which unfortunately returned the same error. Do you have explanation why ?

I'd like to understand the difference with std_logic_vector'('0', '0'), as it looks to me to be the same (ie. indication of the type of the aggregate members).

Anyways, your suggestion works fine. Thanks a lot!

P9

You have to remember, '0' is one of many things:

It is part of the std_logic definition from std_logic_1164:

type std_logic is ('U', 'X', '0', '1'....etc)

it is also part of the bit and character types from std.standard:

type bit is ('0', '1');

type character is (a load of chars, including '0');

so, having '0' on its own is already 1 of 3 things.

Then you have these things:

from ieee.std_logic_1164:

type std_logic_vector is array(natural range <>) of std_logic;

from ieee.numeric_std:

type unsigned is array(natural range <> ) of std_logic;

type signed is array(natural range <> ) of std_logic;

then there is string which is an array of chars, then bit_vector which is an array of bits.

so as soon as you write ('0', '0'), the zeros on their own already have ambiguity, and when you put these ambiguous things together it forms one of many different array types. Without telling the compiler which one it has no idea which one you mean.

Now, what you could have done was have an temporary signal for the qualification:

signal s : std_logic_vector(1 downto 0);

..

(s2, s2) <= s;

s <= ('0', '0');

Here there is no ambiguity, because s is a std_logic_vector, so it can assume that the vector you are making with ('0', '0') is also a std_logic_vector.

--- Quote Start ---

Yesterday I tried something similar :

(s2, s1) <= (std_logic'('0'), std_logic'('0'));

which unfortunately returned the same error. Do you have explanation why ?

--- Quote End ---

because the signed and unsigned types are also arrays of std_logic, although you are saying the zeros are std_logic and not chars or bits, it still doesnt know whether you mean std_logic_vector, signed or unsigned.

OK, I hadn't realized that the external parenthesis were seen as arrays, and that they consequenctly also had a type. It's now all clear to me.

Thanks again for all this precious information

P9