ADPLL using Verilog? Not working!

This a classical example of a gated clock, it's used in the design to clock other modules

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always @(negedge u1 or negedge reset)

begin

if(!reset) u1_star <= 0;

else u1_star <= !u1_star;

end

assign CK = u1 && u1_star;

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Please consult Quartus handbook or FPGA/HDL text books why it's a possible issue. I guess, you can see in timing simulation, if you look sharp.

Generally, I see that there are possible reasons to use a DPLL (digital PLL) respectively ADPLL (all digital PLL) in a design. Apart from practical purpose in some design, it may be used for educational purposes, e.g. to better understand the stuff presented in Best's book.

Please consider, that I didn't yet try to use the code. I didn't say, that the gated clock issue is a reason, why the design doesn't work. There may be a much more basic problem with the points, vernmid mentioned. But it would be a problem, when using the code in a real design.