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Altera_Forum
Honored Contributor
16 years agoThanks for the reply guys,
Well I added <= to the code because, without that it was giving me an error that its expecting "<=" or ';" I am using Verilog. thanksThanks for the reply guys,
Well I added <= to the code because, without that it was giving me an error that its expecting "<=" or ';" I am using Verilog. thanks