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Altera_Forum's avatar
Altera_Forum
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14 years ago

Adding signaltap breaks design, how to debug

Having previously successfully used Signaltap I've re-enabled it after not needing it for a while. Unfortunately when I do that, it breaks my design. The design is for a Cyclone IV and incorporates a PCIe endpoint. I get a bunch of extra warnings which may be significant, but I don't understand them. They include:

Warning: Ignored filter at pcie_compiler_0.sdc(3): refclk_pcie_compiler_0 could not be matched with a port or pin or register or keeper or net

Warning: PLL cross checking found inconsistent PLL clock settings:

Warning: Node: inst1|altpll_component|auto_generated|pll1|clk[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000

Warning: Node: inst1|altpll_component|auto_generated|pll1|clk[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000

Warning: Node: inst1|altpll_component|auto_generated|pll1|clk[2] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000

Warning: Node: inst1|altpll_component|auto_generated|pll1|clk[3] was found missing 1 generated clock that corresponds to a base clock with a period of: 20.000

Any idea how I start debugging this?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    The usual cause of this kind of problem is that your design doesn't meet timing requirements.

    Did you constrain your clocks and I/O properly and does Timequest report any timing violations?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Yes, Timequest reports violations. I've watched the Timequest training videos, and my version of Quartus (10.1 SP1) just doesn't match the examples so I've rather given up on it.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Presuming you don't get the PLL related warnings without SignalTap, it's not a problem of timing violations. It's rather an equivocal setup of clock pathes, that makes the compiler change the PLL connections or placement when SignalTap comes into play.

    The other question is, what do you mean with "braking the design"? Design failure must not necessarily be related to the quoted warnings but can be of course caused by timing violations.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I quoted some of the warnings that appear with signaltap included but aren't there without it.

    The PCIe interface stops working with the signaltap included and the PC wont boot, so it's really broken.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I would compare the clock tree implemented by Quartus with SignalTap with the intended design structure and consider why it can go wrong.