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Altera_Forum's avatar
Altera_Forum
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14 years ago

Adding signaltap breaks design, how to debug

Having previously successfully used Signaltap I've re-enabled it after not needing it for a while. Unfortunately when I do that, it breaks my design. The design is for a Cyclone IV and incorporates a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Presuming you don't get the PLL related warnings without SignalTap, it's not a problem of timing violations. It's rather an equivocal setup of clock pathes, that makes the compiler change the PLL connections or placement when SignalTap comes into play.

The other question is, what do you mean with "braking the design"? Design failure must not necessarily be related to the quoted warnings but can be of course caused by timing violations.