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Altera_Forum
Honored Contributor
8 years agoSolved?
I added a line to my .sdc file to disregard the one failing path (recall the failing pempty signal in my second comment of this thread). After that I didn't have any failing nets (but I did have a few unconstrained I/O like LED's and what-not). After doing that, the design works. My guess (and it is just a wild guess) is that the fitter was trying so hard to get that one net to meet timing that it was messing up something else that may not be properly constrained.