Forum Discussion
Altera_Forum
Honored Contributor
9 years agoAdded a few constraints to .sdc file and the whole design broke?
Hello, I am using the Arria 10 Dev. Board to test out the transceivers. I have a simple design using the Arria 10 Transciever Native PHY with enhanced PCS as well as the associated reset core and...
Altera_Forum
Honored Contributor
9 years agoSolved?
I added a line to my .sdc file to disregard the one failing path (recall the failing pempty signal in my second comment of this thread). After that I didn't have any failing nets (but I did have a few unconstrained I/O like LED's and what-not). After doing that, the design works. My guess (and it is just a wild guess) is that the fitter was trying so hard to get that one net to meet timing that it was messing up something else that may not be properly constrained.