Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Added a few constraints to .sdc file and the whole design broke?

Hello, I am using the Arria 10 Dev. Board to test out the transceivers. I have a simple design using the Arria 10 Transciever Native PHY with enhanced PCS as well as the associated reset core and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

--- Quote Start ---

I should add: when the .sdc file was in place, there was one failing path, but it was a FIFO_PEMPTY (partially empty) signal, which crosses clock boundaries, so I didn't think much of it.

--- Quote End ---

just general notes. you must have sdc for any design. there is no point having a design without sdc.

Your refclk is too fast. Can you explain your clocking scheme.