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Altera_Forum
Honored Contributor
Honored ContributorAdded a few constraints to .sdc file and the whole design broke?
Hello, I am using the Arria 10 Dev. Board to test out the transceivers. I have a simple design using the Arria 10 Transciever Native PHY with enhanced PCS as well as the associated reset core and...
Altera_ForumHonored Contributor
Honored ContributorI should add: when the .sdc file was in place, there was one failing path, but it was a FIFO_PEMPTY (partially empty) signal, which crosses clock boundaries, so I didn't think much of it.
