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Altera_Forum's avatar
Altera_Forum
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13 years ago

Add SignalTap II ,the project won't compilation

Guys:

before i add some signal to the signaltap II ,the whole project compilation is complete , and it work well on FPGA , but after i add some signal to the signaltap the compile came up with error.

the signal i add is a SRAM "wrdata" signal ,the ERROR is like below:

ERROR: Output port 0 of I/O output buffer " pre_syn.bp.Signature_pipe_U_signature_0_~output" must drive a top-level pin

can anyone tell me how to fix this problem? thanks in advance:-P

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    May be because you are tapping an output signal

    You can check once by adding a signal which is driving this output to signaltap instead of adding an output signal
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I am not sure but I have seen this error when you do not connect a pin that can be an input and output (i.e can tristate the output) directly to a pin. Maybe signaltap does not like probing I/O pins.

    C
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    I've had this problem and it seems that SignalTap cant tap a tristate or bidirectional bus. This may be because the synthesiser converts a bidirectional bus into something else (FPGAs don't really do tristate busses internally) and the pre-synthesis nets don't exist.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    May be because you are tapping an output signal

    You can check once by adding a signal which is driving this output to signaltap instead of adding an output signal

    --- Quote End ---

    thank you very much ! it helps