ADC FPGA DDR SDC Constraint

Hello, everyone!!

Have a little issue. Need to write input delay constraint for FPGA. It captures data from LTM9011-14 ADC. Data and clk pins are connected to IDDR module inside the fpga.

CLK is 500MHz.

http://www.alteraforum.com/forum/attachment.php?attachmentid=10133&stc=1

Without input delay constraints have a slack problems : clk signal has longer path delay relative to data path delay.

How can I solve with this proble?