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Altera_Forum
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12 years ago

Accessing SDRAM memory on Terasic DE0-Nano board.

I want to use SDRAM memory located on DE0-Nano board using Verilog (without using Nios). I use http://www.altera.com/support/examples/nios2/exm-avalon-mm.html System placed in the QSYS: htt...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Is that the 'Control Panel' configuration that comes with the DE0 Nano?

If you use the control panel to write to the SDRAM and then reprogram the FPGA with your design, the SDRAM is not going to retain the values written using the control panel. During the FPGA reconfiguration the SDRAM refresh control will stop causing the SDRAM to 'forget' it's memory.

Regards,

Alex