New Contributor
New ContributorThey have two displayport designs available ("DisplayPort UHD Scaler and Mixer Design Example" and "Arria 10 DisplayPort 4Kp60 with Video and Image Processing Pipeline Re-transmit Reference Design"), but neither of them is the one I'm asking about. Both of those are retransmit designs, and this one is a TX-only design.
However, I've just noticed that the document describes the process of generating this design manually, I'll attempt that.
New ContributorGenerating it manually is a bit too complicated for my liking (unless I'm missing something). The process is described as follows:
"Instantiate the DisplayPort Intel® FPGA IP ... Click 'Generate Example Design' ... Modify the generated design example by removing the irrelevant blocks from the top-level design and from the dp_core.qsys file.
Remove the RX sub-system, RX PHY top.... instantiate the relevant Video and Image Processing FPGA IPs. ... Connect the CVO II and TPG II Intel® FPGA IP instances ... "
It sounds simple when described like that. The trouble is that there's no top level qsys file. Most of these connections are in the top-level .v file. Therefore, to complete the process, I need to do all these changes (several dozen wires) directly in Verilog.
