Forum Discussion
Occasional ContributorAbout Timing Constraints
No, as mentioned, set_input/output_delay specifies external delays so the Fitter knows where to place input or output registers to meet timing on the inputs or timing at the downstream device on outputs. set_max/min_delay is a way of specifically saying to the Fitter "I want this path to have a max delay of x and a min delay of y." Both sets of commands affect how the Fitter places and routes things.
Occasional ContributorThank you for answering.
Your detailed explanation was very helpful.
I understand that "set_input_delay/set_output_delay" is the setting of the conditions of the external circuit of the FPGA, and fitting and timing analysis are performed based on these conditions.
Does that mean that it is correct to use "set_max_delay/set_min_delay" when timing the internal path from the output of the FF to the input of the subsequent FF?
Also, what kind of method is there when there is a combinational circuit between FFs when restricting the timing from the output of FF to the input of the subsequent FF?
I'm sorry to trouble you, but it would be helpful if you could teach me.
that's all
sstrellSuper Contributor
You can use set_max/min_delay for internal timing paths as you've suggested, but note that it overrides what the Fitter selects on its own, so you really only need to use them if you have specific timing requirements that the Fitter is not meeting, usually referred to as over-constraining.
set_max/min_delay works between registers, so any combinational logic in between is included in the delay value you specify.
