About timing constraints of ‘in2out’ timing path

Thanks for your help. And this case is only my little example from my all design.

I try to clear this question through Design Compiler in Synopsys, and I have found

the way to solve my constraints question. The setup calculate is as follows:

Required time: Value(max_delay) - Value(output_delay=3ns);

Arrived time: Value(input_delay=3ns) + tdelay;

Setup ensure: Arrived time <= Required time

So, if I want to constraint the tdelay max 2ns, the result is that we should constraint the max_delay 8ns.

set_max_delay 8 -from ina -to outb

No matter at all, thanks. Hope we could commucation more latter.

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I don't see how you found out what the tool is thinking.

set_input_delay has nothing to do with tdelay path. It is meant for register path only, so is set_output_delay. And in both cases it has nothing to do with concept of pure delay.

set_input_delay is information to the tool about data/clock offset arriving at pins. set_output_delay is information to the tool about allowed range of data/clock offset ejected at output pin.

The path of tdelay is comb. from pin to pin and I suppose it will be dealt with independant of register path. Whether you get it or not is up to your luck but still I don't understand the merits of your approach from basic design perspective. May be you tell us what is the purpose of your constraints...

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