Forum Discussion
Occasional ContributorAbout the concept of "set_output_delay constraint"
When you mention 2), I believe this is the question you are referring to:
"2) Depending on the values of tsu_ext and th_ext, the result of the formula may be "output delay max < output delay min", but does that mean there is no problem?"
Yes, it is possible for the setting value of set_output_delay -min to be larger than the setting value of set_output_delay -max depending on the setup/hold time of the downstream device/ external circuit.
If the downstream device has a shorter setup time requirement, then the set_output_delay -min value can be larger than the set_output_delay -max value. This is because a larger delay would be needed to ensure that the output signal meets the shorter setup time requirement.
Conversely, if the downstream device has a shorter hold time requirement, then the set_output_delay -max value can be larger than the set_output_delay -min value. This is because a smaller delay would be needed to ensure that the output signal meets the shorter hold time requirement.
In summary, the setting values of set_output_delay -min and -max can vary depending on the timing requirements of the downstream device. It is important to carefully analyze the timing requirements of the entire system to determine appropriate delay values for each constraint.
Hope that helps to clarify. : )
Best Regards,
Richard Tan
Occasional ContributorThank you for answering.
"1)" was intended to ask about the concept of set_output_delay -max, but the sentence was cut off in the middle. very sorry.
It would be helpful if you could teach set_output_delay -max in the same way.
As for "2)", I asked whether the setting value of set_output_delay -min may be larger than the setting value of set_output_delay -max depending on the setup/hold time of the downstream device, but "1)" It was a meaningless question because it was a description of the premise that there was a description of set_output_delay -max in . very sorry.
Thank you for showing the calculation formula.
I'm checking because the machine translation doesn't seem to work well, but the formula you provided is
Tclk2(max) : Clock arrival time to downstream device
Tclk1ext(min): clock arrival time to target FPGA
Is that all right?
Sorry for the inconvenience, but thank you in advance.
