Forum Discussion
Occasional ContributorAbout the concept of "set_output_delay constraint"
When you mention 2), I believe this is the question you are referring to:
"2) Depending on the values of tsu_ext and th_ext, the result of the formula may be "output delay max < output delay min", but does that mean there is no problem?"
Yes, it is possible for the setting value of set_output_delay -min to be larger than the setting value of set_output_delay -max depending on the setup/hold time of the downstream device/ external circuit.
If the downstream device has a shorter setup time requirement, then the set_output_delay -min value can be larger than the set_output_delay -max value. This is because a larger delay would be needed to ensure that the output signal meets the shorter setup time requirement.
Conversely, if the downstream device has a shorter hold time requirement, then the set_output_delay -max value can be larger than the set_output_delay -min value. This is because a smaller delay would be needed to ensure that the output signal meets the shorter hold time requirement.
In summary, the setting values of set_output_delay -min and -max can vary depending on the timing requirements of the downstream device. It is important to carefully analyze the timing requirements of the entire system to determine appropriate delay values for each constraint.
Hope that helps to clarify. : )
Best Regards,
Richard Tan
Super Contributor1) Not quite understanding what you are saying here, but set_output_delay -min lets you specify the minimum external delay for data to reach the downstream device and remain stable long enough to meet that device's hold timing requirement. Based on this value, the compiler adjusts tco of the output to meet the requirement.
2) "Larger" than what? But yes it is based on the external path delay and the th of the downstream device to calculate the hold required time for that device.
3) Your equation seems off. The clock skew calculation doesn't look correct. (EDIT: oh, your definitions of clk1 and clk2 are swapped from what I have below so they are the same.) Should be:
output delay min = Data trace (min) - Board clock skew (max) – Th
= (Tdata_PCB(min) + TCL (delay due to capacitive loading if you want to include it)) - (Tclk2(max) – Tclk1ext(min) ) - Th
As for your interpretation, it seems correct but you should always have set_output_delay -min in your .sdc no matter the value to ensure the path does not appear as unconstrained.
