Forum Discussion
Occasional ContributorAbout SignalTap
In most cases, you choose a clock that is in the same clock domain with the signal that you are looking at. But there is no requirement for that. Sometimes you might use a faster clock domain for a slower signal, to get a higher sampling rate.
You can use the fastest clock available to get the best results.
Refer to the Timing Analysis section of the Compilation Report for the maximum frequency of the logic analyzer clock.
Occasional ContributorThank you for answering.
Step 4 is to specify the signal configuration and trigger to be monitored.
This means that there is no problem with the method of creating the stp1.stp file itself.
The current problem here is the following.
1) When I check the signal output to the IO pin as a monitor with an oscilloscope, it works properly, but when I look at it with Signal Tap, it doesn't show the same waveform as the oscilloscope. (Signal Tap does not look directly at the output pin, but looks at the signal connected to it.)
2) The system clock is 20MHz (generated by the PLL) and what you want to check is its synchronization circuit. The internal operation runs at 1MHz, but the timing generation etc. are performed with a pulse of 50ns width. If you try to trigger with this 50ns pulse, the trigger will not work. It is the same as 1) that it works normally when output to the IO pin as a monitor.
It is recommended that the Signal Tap clock be at least twice the signal, but in the above case, does the Signal Tap clock need to be at least 40MHz?
I will check the presented materials from now on, but if you have any suggestions, it would be helpful if you could let me know.
