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Yamada1's avatar
Yamada1
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

About SignalTap

I'm trying to debug with signal tap, but I can't see the signal as I expected. It would be helpful if you could give me advice on how to use the signal tap. I am using Quartus Prime Standard Edit...
  • RichardT_altera's avatar
    RichardT_altera
    3 years ago

    In most cases, you choose a clock that is in the same clock domain with the signal that you are looking at. But there is no requirement for that. Sometimes you might use a faster clock domain for a slower signal, to get a higher sampling rate.

    You can use the fastest clock available to get the best results.

    Refer to the Timing Analysis section of the Compilation Report for the maximum frequency of the logic analyzer clock.


RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
3 years ago

I assume Step 4 Specify the data - mean to set the trigger condition and the signal configuration. If so, I think so far so good.

Btw, we have a tutorials on "SignalTap with Verilog Designs"

Find "Signal Tap Logic Analyzer " @ https://fpgacademy.org/tutorials.html > Click Verilog or VHDL to download the file.


You can go through the tutorial to get familiar with it.


There also instructor-led class on Signal Tap, next week. (although the time may not be friendly but it is highly recommended)

https://learning.intel.com/Developer/learn/course/internal/view/classroom/1066/signal-tap


Best Regards,

Richard Tan


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.