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Altera_Forum's avatar
Altera_Forum
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12 years ago

About signal and variable

I just start using VHDL for one month, I am a little confused by signal and variable.

I read the textbook, I know the difference between them like:

Variable is a local one can be used inside process where it is declaration.

Variable can be assigned an initial value while signal can but only in simulation.

Both of them can be synthesised.

But I am not clear is when I should use signal, and when I should use variable. Is there any rules I should follow? If someone can take some simple examples, that will be very helpful for me to understand.

Thanks in advance.

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Thats correct. you dont need variables in most cases. The only time you may want to use them is to break down complicated assigments to make the more readible, or you will have to use them in functions and procedures (again, mainly used for readability).

    But when it comes to testbenches - go wild. (ie. variables become very useful).