--- Quote Start ---
That is correct Kaz, and hence why I suggest sticking with signals until you're confident with VHDL. Variable placement makes all the difference when it comes to infering logic, getting code in the wrong order can cause you problems or infered latches, or just no logic at all.
--- Quote End ---
Indeed. In all the so many years of work I have never needed to use variable except once. Here its is:
-- basically a clocked process
variable counter : unsigned(12 downto 0) := (others => '0');
...
counter := counter + unsigned(increment);
if counter > 3071 then -- wrap up at overflow
counter := counter - to_unsigned(3072,12);
end if;
addr <= std_logic_vector(counter);
...
It is an accumulator that adds increment value modulo 3072(for NCO etc). The counter must be checked for overflow but should not overflow! instead it should wrap up. So it needs to be prejudged. Though one can use a second counter(that looks ahead) but a variable is useful here.
if you use signal it will overflow first then wrap up which is not right in this case.
Honored Contributor
