About signal and variable

That is correct Kaz, and hence why I suggest sticking with signals until you're confident with VHDL. Variable placement makes all the difference when it comes to infering logic, getting code in the wrong order can cause you problems or infered latches, or just no logic at all.

IIRC, this code could be the cause for some problems as the synthesisor is likely to infer a constant, whereas the simulation would show a counter.

process(clk)
  variable : a := integer 0;
begin
  if rising_edge(clk) then
    a := a + 1;
    op <= a;
  end if;
end process;

Because the register element lives with the op signal, not with a, and as a is initialised to 0, there is no storage associated with a and hence drives a constant 1.

but if you changed it to

a := op + 1;

it would work fine, as a is the sum of the register and 1.