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Thanks very much, both of you.
I can try to avoid using variables, but this may not help in long term since if I keep avoid it, how can I know how to use it?
kaz, your conclusion is very interesting. Since variable can be only used in a process (where it is declared). If this process is a sequential logic (sensitivity list is a clock and trigger by edge) , then signal is used for registers while variables is used for combinatorial logic. But if this is already a combinatorial logic process, then signal and variable will be same. Is that my understanding basically right?
Thanks very much.
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Basically I think so.
Let me reword my view of variable Versus signal within a clocked process.
When node A is signal then A <= B and C; infers a circuit of B and C followed by register A (comb. then register).
when node A is variable then A:= B and C; infers a circuit of B and C => A (comb. only)
Whether then you get a register at final compilation depends.
If value of A variable is used later in another statement within process e.g.
A := B and C;
D <= A;
then no register is inferred to save A. comb. of B and C => A is inferred followed by D register.
If value of (A) is used before its assignment e.g.
D <= A;
A := B and C;
then it implies registering node A to start of process then applying it to D. Thus I assume you may get two registers now D and that outputting A.
In non clocked process(comb) I don't expect much difference between using signal or variable but behaviorally it remains that the variable is meant to acquire its value without update at end of process.
All above is my personal view and may be verified by simple experiments(that I haven't done)
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