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I just start using VHDL for one month, I am a little confused by signal and variable.
I read the textbook, I know the difference between them like:
Variable is a local one can be used inside process where it is declaration.
Variable can be assigned an initial value while signal can but only in simulation.
Both of them can be synthesised.
But I am not clear is when I should use signal, and when I should use variable. Is there any rules I should follow? If someone can take some simple examples, that will be very helpful for me to understand.
Thanks in advance.
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The way I think of a variable (inside a vhdl process at least) is that it allows combinatorial parts(and hence quick decision).
Remember every signal assignment inside a clocked process infers logic of your assignment right hand followed by a register. for example:
value1 <= temp + 1; means an adder followed by the register value1.
But at times you might need value1 to get the temp + 1 before going through a register delay. In this case you declare as variable then:
value1 := temp + 1; gets adder result for target without delay.
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