About signal and variable

Yes, as a beginner, only use signals. variables will confuse you.

The actual difference is that signals are only scheduled to be updated when a process suspends and takes the last value assigned to it, but a variable is updated immediatly. These differences in behavior can lead to things that look odd to people that dont understand.

signal a : integer := 0;  --there is nothing wrong with giving an initial value to a signal. It should synthesise fine as the power up value
process(clk)
  variable b : integer := 0;
begin
  if rising_edge(clk) then
    a <= 10;
    a <= a + 90;
    a <= a + 1;
    b := 10;
    b := b + 90;
    b := b + 1;
  end if;
end process;

In this code, if you simulated it, you would see a start at 0 and increment by 1 on every clock cycle because the assignmnet of 10 and +90 are overriden by the a+1 assignment. b would just be constant at 101 forever. Variables can be used to synthesise the same hardware as signals (mostly) but then your code ordering has much more of an effect.

So - general rule - dont use variables until you know more about VHDL. Stick with signals for now.